Z8S18020FSC Datasheet, PDF (12/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
ARCHITECTURE
The Z180^® combines a high-performance CPU core with a
variety of system and I/O resources useful in a broad
range of applications. The CPU core consists of five func-
tional blocks: clock generator, bus state controller, Inter-
rupt controller, memory management unit (MMU), and the
central processing unit (CPU). The integrated I/O resourc-
es make up the remaining four function blocks: direct
memory access (DMA) control (2 channels), asynchro-
nous serial communication interface (ASCI, 2 channels)
programmable reload timers (PRT, 2 channels), and a
clock serial I/O (CSIO) channel.
Clock Generator. Generates system clock from an exter-
nal crystal or clock input. The external clock is divided by
two or one and provided to both internal and external de-
vices.
Bus State Controller. This logic performs all of the status
and bus control activity associated with both the CPU and
some on-chip peripherals. This includes wait-state timing,
reset cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller. This logic monitors and prioritizes
the variety of internal and external interrupts and traps to
provide the correct responses from the CPU. To maintain
compatibility with the Z80^® CPU, three different interrupts
modes are supported.
Memory Management Unit. The MMU allows the user to
“map” the memory used by the CPU (logically only 64KB)
into the 1 MB addressing range supported by the
Z80180/Z8S180/Z8L180. The organization of the MMU
object code maintains compatibility with the Z80 CPU,
while offering access to an extended memory space. This
is accomplished by using an effective “common area-
banked area” scheme.
Zilog
Central Processing Unit. The CPU is microcoded to pro-
vide a core that is object-code compatible with the Z80
CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiply. The core has been modified to al-
low many of the instructions to execute in fewer clock cy-
cles.
DMA Controller. The DMA controller provides high speed
transfers between memory and I/O devices. Transfer op-
erations supported are memory-to-memory, memory
to/from I/O, and I/O-to-I/O. Transfer modes supported are
request, burst, and cycle steal. DMA transfers can access
the full 1 MB address range with a block length up to 64
KB, and can cross over 64K boundaries.
Asynchronous Serial Communication Interface (AS-
CI). The ASCI logic provides two individual full-duplex
UARTs. Each channel includes a programmable baud rate
generator and modem control signals. The ASCI channels
can also support a multiprocessor communication format
as well as break detection and generation.
Programmable Reload Timers (PRT). This logic consists
of two separate channels, each containing a 16-bit counter
(timer) and count reload register. The time base for the
counters is derived from the system clock (divided by 20)
before reaching the counter. PRT channel 1 provides an
optional output to allow for waveform generation.
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PRELIMINARY
DS971800401