Z8S18020FSC Datasheet, PDF (30/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
ø
31
32
/INTi
33
/NMI
/MI *1
/IORQ *1
Date IN *1
/MREQ *2
/RFSH *2
35
34
/BUSREQ
/BUSACk
ADDRESS
DATA
/MREQ /RD
/WR, /IORQ
/HALT
10
30
39
41
40
28
15
14
29
16
42
34
35
36
37
38
38
43^*3
44
Notes:
1. During /INT₀ acknowledge cycle.
2. During refresh cycle.
3. Output buffer is off at this point.
Figure 21. CPU Timing
(/INT₀ Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode,
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
Zilog
1-30
PRELIMINARY
DS971800401