Z8S18020FSC Datasheet, PDF (31/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
φ
ADDRESS
IROQ
RD
WR
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
I/O Read Cycle
I/O Write Cycle
T₁
T₂
T_w
T₃
T₁
T₂
T_w
T₃
1
28
29
28
29
9
13
22
25
CPU Timing (IOC=0)
I/O Read Cycle
I/O Write Cycle
Figure 22. CPU Timing (/IOC = 0)
(I/O Read Cycle, I/O Write Cycle)
ø
/DREQi
(at level sense)
/DREQi
(at level sense)
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T₁
T₂
T_W
T₃
T₁
45 46^*1
*2
45 46
/TENDi
ST
47
*3 ₁₇
*4 ₁₈
48
1. t_DRQS and t_DHQH are specified for the rising edge of clock followed by T₃.
*2. t_DRQS and t_DHQH are specified for the rising edge of clock.
*3. DMA cycle starts.
*4. CPU cycle starts
Figure 23. DMA Control Signals
DS971800401
PRELIMINARY
1-31