Z8S18020FSC Datasheet, PDF (38/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
The following paragraphs explain the various functions of
the ASCI registers.
ASCI Transmit Register 0. When the ASCI Transmit
Register receives data from the ASCI Transmit Data Reg-
ister (TDR), the data is shifted out to the TxA pin. When
transmission is completed, the next byte (if available) is
automatically loaded from TDR into TSR and the next
transmission starts. If no data is available for transmission,
TSR IDLEs by outputting a continuous High level. This reg-
ister is not program accessible
ASCI Transmit Data Register 0,1 (TDR0, 1: I/O address
= 06H, 07H). Data written to the ASCI Transmit Data Reg-
ister is transferred to the TSR as soon as TSR is empty.
Data can be written while TSR is shifting out the previous
byte of data. Thus, the ASCI transmitter is double buffered.
Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation will not be af-
fected by this read operation
ASCI Receive Shift Register 0,1 (RSR0,1). This register
receives data shifted in on the RxA pin. When full, data is
automatically transferred to the ASCI Receive Data Regis-
ter (RDR) if it is empty. If RSR is not empty when the next
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
ASCI Receive Data FIFO 0,1 (RDR0, 1:I/O Address = 08H,
09H). The ASCI Receive Data Register is a read-only reg-
ister. When a complete incoming data byte is assembled
in RSR, it is automatically transferred to the 4 character
Receive Data First-In First-Out (FIFO) memory. The oldest
character in the FIFO (if any) can be read from the Receive
Data Register (RDR). The next incoming data byte can be
shifted into RSR while the FIFO is full. Thus, the ASCI re-
ceiver is well buffered.
ASCI STATUS FIFO
This 4 entry FIFO contains Parity Error, Framing Error, Rx
Overrun, and Break status bits associated with each char-
acter in the receive data FIFO. The status of the oldest
character (if any) can be read from the ASCI status regis-
ters as described below
1-38
PRELIMINARY
DS971800401