Z8S18020FSC Datasheet, PDF (37/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
IASCI REGISTER DESCRIPTION
TXA₀
RXA₀
RTS₀
CTS₀
DCD₀
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Shift Register*
Ch 0: TSR0
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Shift Register*
Ch 0: RSR0 (8)
ASCI Control Register A
Ch 0: CNTLA0 (8)
ASCI Control Register B
Ch 0: CNTB0 (8)
ASCI Status FIFO
Ch 0
ASCI Status Register
Ch 0: STAT0 (8)
ASCI Extension Control Reg.
Ch 0: ASEXT0 (7)
ASCI Time Constant Low
Ch 0: ASTCOL (8)
ASCI Time Constant High
Ch 0: ASTCOH (8)
CKA₀
CKA₁
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Internal Address/Data Bus
1
Interrupt Request
ASCI
Control
ASCI Transmit Data Register
Ch 1: TDR1
ASCI Transmit Shift Register*
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 1: RDR1
ASCI Receive Shift Register*
Ch 1: RSR1 (8)
ASCI Control Register A
Ch 1: CNTLA1 (8)
ASCI Control Register B
Ch 1: CNTB1 (8)
ASCI Status FIFO
Ch 1
ASCI Status Register
Ch 1: STAT1 (8)
ASCI Extension Control Reg.
Ch 1: ASEXT1 (5)
ASCI Time Constant Low
Ch 1: ASTCIL (8)
ASCI Time Constant High
Ch 1: ASTCIH (8)
TXA₁
RXA₁
CTS₁
Baud Rate
Generator 0
φ
Baud Rate
Generator 1
Note: *Not Program
Accessible.
Figure 32. ASCI Block Diagram
DS971800401
PRELIMINARY
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