Z8S18020FSC Datasheet, PDF (63/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
MMU BANK BASE REGISTER (BBR).
Mnemonic BBR
Address 39
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
BBR specifies the base address (on 4 KB boundaries)
1 ^{used to generate a 19-bit physical address for Bank Area}
accesses. All bits of BBR are reset to 0 during RESET.
7
6
5
4
3
2
1
0
Bit
BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 80. MMU Bank Base Register (BBR: I/O Address = 39H)
MMU COMMON/BANK AREA REGISTER (CBAR).
Mnemonic CBAR
Address 3A
CBAR specifies boundaries within the
Z80180/Z8S180/Z8L180 64 KB logical address space for
up to three areas; Common Area), Bank Area and Com-
mon Area 1.
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH)
Bit
7
6
5
4
3
2
1
0
CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 81. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3-CA0:CA (bits 7-4). CA specifies the start (Low) ad-
dress (on 4 KB boundaries) for the Common Area 1. This
also determines the last address of the Bank Area. All bits
of CA are set to 1 during RESET.
BA-BA0 (bits 3-0). BA specifies the start (Low) address
(on 4 KB boundaries) for the Bank Area. This also deter-
mines the last address of the Common Area 0. All bits of
BA are set to 1 during RESET.
DS971800401
PRELIMINARY
1-63