Z8S18020FSC Datasheet, PDF (20/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
IDLE Mode
φ
BUSREQ
9.5 Cycle Delay until BUSACK Asserted
BUSACK
Bus RELEASE Mode IDLE Mode
TX
TX
Zilog
A₁₉-A₀
HALT
M1
High
Low
FFFFFH
High Impedance
Figure 16. Bus Granting to External Master in IDLE Mode
FFFFFH
STANDBY Mode (With or Without QUICK RECOVERY).
Software can put the Z80180/Z8S180/Z8L180 into this
mode by setting the IOSTOP bit (ICR5) to 1 and CCR6 to
1, and executing the SLP instruction. This mode stops the
on-chip oscillator and thus draws the least power of any
mode, less than 10µµA.
As with IDLE mode, the Z80180/Z8S180/Z8L180 will leave
STANDBY mode in response to a Low on RESET or on
NMI, or a Low on INT0-2 that is enabled by a 1 in the cor-
responding bit in the INT/TRAP Control Register, and will
grant the bus to an external master if the BREXT bit in the
CPU Control Register (CCR5) is 1. But the time required
for all of these operations is greatly increased by the need
to restart the on-chip oscillator and ensure that it has sta-
bilized to square-wave operation.
When an external clock is connected to the EXTAL pin
rather than a crystal to the XTAL and EXTAL pins, and the
external clock runs continuously, there is little need to use
STANDBY mode because there is no time required to re-
start the oscillator, and other modes restart faster. Howev-
er, if external logic stops the clock during STANDBY mode
(for example, by decoding HALT Low and M1 High for sev-
eral clock cycles), then STANDBY mode can be useful to
allow the external clock source to stabilize after it is re-en-
abled.
When external logic drives RESET Low to being a
Z80180/Z8S180/Z8L180 out of STANDBY mode, and a
crystal is used or an external clock source has been
stopped, the external logic must hold RESET Low until the
on-chip oscillator or external clock source has restarted
and stabilized.
The clock stability requirements of the
Z80180/Z8S180/Z8L180 are much less in the divide-by-
two mode that's selected by a Reset sequence and there-
after controlled by the Clock Divide bit in the CPU Control
Register (CCR7). Because of this, software should:
a. Program CCR7 to 0 to select divide-by-two mode,
before the SLP instruction that enters STANDBY
mode, and.
b. After a Reset, interrupt or in-line restart after the
SLP 01 instruction, delay programming CCR7
back to 1 to set divide-by-one mode, as long as
possible to allow additional clock stabilization
time.
If software sets CCR6 to 1 before the SLP instruction plac-
es the MPU in STANDBY mode, the value in the CCR3 bit
determines how long the Z80180/Z8S180/Z8L180 will wait
for oscillator restart and stabilization when it leaves
STANDBY mode due to an external interrupt request. If
CCR3 is 0, the Z80180/Z8S180/Z8L180 waits 217
(131,072) clock cycles, while if CCR3 is 1, it waits only 64
clock cycles. The latter is called QUICK RECOVERY
mode. The same delay applies to granting the bus to an
1-20
PRELIMINARY
DS971800401