Z8S18020FSC Datasheet, PDF (61/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
3nd Opcode ^Memory
Fetch Cycle Read Cycle
Restart
from 0000H
1
Opcode
PC Stacking
Fetch Cycle
φ
A₀-A₁₈ (A₁₉)
D₀-D₇
M1
MREQ
RD
WR
T₁ T₂ T₃ T₁ T₂ T_TP T₃ T_i T_i T_i T_i T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ ^T₃
PC
IX + d, IY + d
Undefined
Opcode
SP-1
PC-1_H
SP-2
PC-1_L
0000H
Figure 77. TRAP Timing-3^rd Opcode Undefined
REFRESH CONTROL REGISTER
Mnemonic RCR
Address 36
7- 6
-- --
54
-- --
32
-- --
10
-- --
REFE
REFW
Cyc0
Cyc1
Reserved
Figure 78. Refresh Control Register
(RCA: I/O Address = 36H)
The RCR specifies the interval and length of refresh cy-
cles, while enabling or disabling the refresh function.
REFE: Refresh Enable (bit 7). REFE = disables the re-
fresh controller while REFE = 1 enables refresh cycle in-
sertion. REFE is set to 1 during RESET.
REFW: Refresh Wait (bit 6). REFW = 0 causes the re-
fresh cycle to be two clocks in duration. REFW = 1 causes
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (TRW). REFW is set to 1 during RESET.
CYC1, 0: Cycle Interval (bit 1,0). CYC1 and CYC0 spec-
ify the interval (in clock cycles) between refresh cycles. In
the case of dynamic RAMs requiring 128 refresh cycles ev-
ery 2 ms (0r 256 cycles in every 4 ms), the required refresh
interval is less than or equal to 15.625 µs. Thus, the under-
lined values indicate the best refresh interval depending
on CPU clock frequency. CYC0 and CYC1 are cleared to
0 during RESET (see Table 14).
DS971800401
PRELIMINARY
1-61