Z8S18020FSC Datasheet, PDF (21/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
external master during STANDBY mode, when the BREXT enabled in the INT/TRAP Control Register, but the IEF, bit
bit in the CPU Control Register (CCR5) is 1.
is 0 due to a DI instruction, the processor restarts by exe-
1 ^{cuting the instruction(s) following the SLP instruction. If}
As described previously for SLEEP and IDLE modes, _{INT0, or INT1 or 2 goes inactive before the end of the clock}
when a Z80180/Z8S180/Z8L180 leaves STANDBY mode _{stabilization delay, the Z80180/Z8S180/Z8L180 stays in}
due to NMI Low, or when it leaves STANDBY mode due to _{STANDBY mode.}
an enabled INTO-2 low when the IEF, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the Figure 17 shows the timing for leaving STANDBY mode
return address being that of the instruction following the due to an interrupt request. Note that the
SLP instruction. If the Z80180/Z8S180/Z8L180 leaves Z80180/Z8S180/Z8L180 takes either 64 or 217 (131,072)
STANDBY mode due to an external interrupt request that's clocks to restart, depending on the CCR3 bit.
STANDBY Mode
Opcode Fetch or Interrupt
Acknowledge Cycle
T₁
T₂
T₃
T₄
φ
2¹⁷ or 64 Cycle Delay from INTi Asserted
NMI
or
INTi
A₁₉-A₀
HALT
FFFFFH
M1
Figure 17. Z80180/Z8S180/Z8L180 STANDBY Mode Exit due to External Interrupt
While the Z80180/Z8S180/Z8L180 is in STANDBY mode,
it will grant the bus to an external master if the BREXT bit
(CCR5) is 1. Figure 18 shows the timing of this sequence.
Note that the part takes 64 or 217 (131,072) clock cycles
to grant the bus depending on the CCR3 bit.
The latter (non-Quick-Recovery) case may be prohibitive
for many “demand driven” external masters. If so, QUICK
RECOVERY or IDLE mode can be used.
DS971800401
PRELIMINARY
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