Z8S18020FSC Datasheet, PDF (45/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
Timer Reload Register 0L
RLDR0L
0E H
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Timer Reload Register 0H
RLDR0H
0F H
1
76
-- --
54 32
-- -- -- --
10
-- ^--
76
-- --
54 32
-- -- -- --
10
-- ^--
Timer Reload Data
Figure 44. Timer Reload Register Low
Timer Reload Data
Figure 45. Timer Reload Register Channel
TIMER CONTROL REGISTER (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status.
It also controls enabling and disabling of down counting
and interrupts along with controlling output pin A18/TOUT
for PRT1.
Bit
7
TIF1
R
6
TIF0
R
5
TIE1
R/W
4
3
2
1
0
TIE0
R/W
TOC1
R/W
TOC0
R/W
TDE1
R/W
TDE0
R/W
Figure 46. Timer Control Register (TCR: I/O Address = 10H)
TIF1: Timer Interrupt Flag 1 (bit 7). When TMDR1 decre-
ments to 0, TIF1 is set to 1. This generates an interrupt re-
quest if enabled by TIE1 = 1. TIF1 is reset to 0 when TCR
is read and the higher or lower byte of TMDR1 is read. Dur-
ing RESET, TIF1 is cleared to 0.
TIF0: Timer Interrupt Flag 0 (bit 6). When TMDR0 decre-
ments to 0, TIF0 is set to 1. This generates an interrupt re-
quest if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR
is read and the higher or lower byte of TMDR0 is read. Dur-
ing RESET, TIF0 is cleared to 0.
TIE1: Timer Interrupt Enable 1 (bit 5). When TIE0 is set
to 1, TIF1 = 1 generates a CPU interrupt request. When
TIE0 is reset to 0, the interrupt request is inhibited. During
RESET, TIE0 is cleared to 0.
TOC1, 0: Timer Output Control (bits 3, 2). TOC1 and
TOC0 control the output of PRT1 using the multiplexed
TOUT/DREQ pin as shown in Table 11. During RESET,
TOC1 and TOC0 are cleared to 0. If bit 3 of the IAR1B reg-
ister is 1, the TOUT function is selected. By programming
TOC1 and TOC0, the TOUT/DREQ pin can be forced
High, Low, or toggled when TMDR1 decrements to 0.
Table 8. Timer Output Control
TOC1 TOC0
Output
0
0 Inhibited The TOUT/DREQ pin is not
affected by the PRT.
0
1 Toggled If bit 3 of IAR1B is 1, the
1
0
1
1
0
TOUT/DREQ pin is toggles or
1
set Low or High as indicated.
DS971800401
PRELIMINARY
1-45