Z8S18020FSC Datasheet, PDF (60/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Opcode is fetched during the interrupt acknowledge cycle
for INT₀ when Mode 0 is used.
When a TRAP interrupt occurs, the
Z80180/Z8S180/Z8L180 operates as follows:
1. The TRAP bit in the Interrupt TRAP/Control (ITC)
register is set to 1.
2. The current PC (Program Counter) value, reflecting
the location of the undefined Opcode, is saved on the
stack.
3. The Z80180/Z8S180/Z8L180 vectors to logical
address 0. Note that if logical address 0000H is
mapped to physical address 00000H, the vector is the
same as for RESET. In this case, testing the TRAP bit
Zilog
in ITC will reveal whether the restart at physical
address 00000H was caused by RESET or TRAP.
All TRAP interrupts occur after fetching an undefined sec-
ond Opcode byte following one of the “prefix” Opcodes
CBH, DDH, EDH, or FDH, or after fetching an undefined
third Opcode byte following one of the “double prefix” Op-
codes DDCBH or FDCBH.
The state of the Undefined Fetch Object (UFO) bit in ITC
allows TRAP software to correctly “adjust” the stacked PC,
depending on whether the second or third byte of the Op-
code generated the TRAP. If UFO=0, the starting address
of the invalid instruction is equal to the stacked PC-1. If
UFO=1, the starting address of the invalid instruction is
equal to the stacked PC-2.
φ
A₀-A₁₈ (A₁₉)
D₀-D₇
M1
MREQ
RD
WR
Restart
from 0000H
2nd Opcode
Fetch Cycle
PC Stacking
Opcode
Fetch Cycle
T₁ T₂ T₃ T_TP T_i T_i T_i T_i T_i T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ T₃
PC
Undefined
Opcode
SP-1
PC_H
SP-2
PC_L
0000H
Figure 76. TRAP Timing-2^nd Opcode Undefined
1-60
PRELIMINARY
DS971800401