Z8S18020FSC Datasheet, PDF (16/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
T₁
T₂
T₃
T₁
T₂
T₃
φ
/WR
/M1
Write into OMCR
Opcode Fetch
Figure 10. M1 Temporary Enable Timing
Zilog
IOC. This bit controls the timing of the /IORQ and /RD sig- When /IOC=1, the /IORQ and /RD signals function the
nals. It is set to 1 by reset.
same as the Z64180 (Figure 11).
T₁
φ
/IORQ
/RD
T₂
T_W
T₃
/WR
Figure 11. I/O Read and Write Cycles with IOC = 1
When /IOC = 0, the timing of the /IORQ and RD signals go active as a result of the rising edge of T2. (Figure 12.)
match the timing of the Z80. The /IORQ and /RD signals
T₁
φ
/IORQ
/RD
/WR
T₂
T_W
T₃
Figure 12. I/O Read and Write Cycles with IOC = 0
1-16
PRELIMINARY
DS971800401