Z8S18020FSC Datasheet, PDF (14/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Clocked Serial I/O (CSI/O). The CSIO channel provides a
half-duplex serial transmitter and receiver. This channel
can be used for simple high-speed data connection to an-
other microprocessor or microcomputer. TRDR is used for
both CSI/O transmission and reception. Thus, the system
design must ensure that the constraints of half-duplex op-
eration are met (Transmit and Receive operation cannot
occur simultaneously). For example, if a CSI/O transmis-
Zilog
sion is attempted while the CSI/O is receiving data, a
CSI/O will not work. Also note that TRDR is not buffered.
Therefore, attempting to perform a CSI/O transmit while
the previous transmit data is still being shifted out causes
the shift data to be immediately updated, thereby corrupt-
ing the transmit operation in progress. Similarly, reading
TRDR while a transmit or receive is in progress should be
avoided.
Internal Address/Data Bus
φ
TXS
RXS
CSI/O Transmit/Receive
Data Register:
TRDR (8)
CSI/O Control Register:
CNTR (8)
Baud Rate
Generator
CKS
Interrupt Request
Figure 7. CSIO Block Diagram
OPERATION MODES
Z80^® versus 64180 Compatibility. The
Z80180/Z8S180/Z8L180 is descended from two different
“ancestor” processors, Zilog's original Z80 and the Hitachi
64180. The Operating Mode Control Register (OMCR),
shown in Figure 8, can be programmed to select between
certain Z80 and 64180differences.
D7 D6 D5 -- -- -- -- --
Reserved
/IOC (R/W)
/M1TE (W)
M1E (R/W)
Figure 8. Operating Control Register
(OMCR: I/O Address = 3EH)
M1E (M1 Enable). This bit controls the M1 output and is
set to a 1 during reset.
When M1E=1, the M1 output is asserted Low during the
opcode fetch cycle, the INT0 acknowledge cycle, and the
first machine cycle of the NMI acknowledge.
On the Z80180/Z8S180/Z8L180, this choice makes the
processor fetch an RETI instruction once, and when fetch-
ing an RETI from zero-wait-state memory will use three
clock machine cycles, which are not fully Z80-timing com-
patible but are compatible with the on-chip CTCs.
When M1E=0, the processor does not drive M1 Low during
instruction fetch cycles, and after fetching an RETI instruc-
tion once with normal timing, it goes back and re-fetches
the instruction using fully Z80-compatible cycles that in-
clude driving M1 Low. This may be needed by some exter-
nal Z80 peripherals to properly decode the RETI instruc-
tion. Figure 9 and Table 4 show the RETI sequence when
M1E=0.
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PRELIMINARY
DS971800401