Z8S18020FSC Datasheet, PDF (39/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
ASCI CHANNEL CONTROL REGISTER A
ASCI Control Register A 0 (CNTLA0: I/O Address = 00H)
Bit
7
6
5
4
3
2
1
0
1
MPE
RE
MPBR/
TE
RTS0 EFR
MOD2 MOD1 MOD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
MPE
R/W
ASCI Control Register A 1 (CNTLA1: I/O Address = 01H)
6
5
4
3
2
1
MPBR/
RE
TE _{CKA1D EFR}
MOD2 MOD1
R/W
R/W
R/W
R/W
R/W
R/W
0
MOD0
R/W
Figure 33. ASCI Channel Control Register A
MPE: Multi-Processor Mode Enable (bit 7). The ASCI
has a multiprocessor communication mode that utilizes an
extra data bit for selective communication when a number
of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set to
1. If multiprocessor mode is not selected (MP bit in CNTLB
= 0), MPE has no effect. If multiprocessor mode is select-
ed, MPE enables or disables the “wake-up” feature as fol-
lows. If MBE is set to 1, only received bytes in which the
MPB (multiprocessor bit) = 1 can affect the RDRF and er-
ror flags. Effectively, other bytes (with MPB = 0) are “ig-
nored” by the ASCI. If MPE is reset to 0, all bytes, regard-
less of the state of the MPB data bit, affect the REDR and
error flags. MPE is cleared to 0 during RESET.
RE: Receiver Enable (bit 6). When RE is set to 1, the
ASCI transmitter is enabled. When TE is reset to 0, the
transmitter is disables and any transmit operation in
progress is interrupted. However, the TDRE flag is not re-
set and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode during RESET.
TE: Transmitter Enable (bit 5). When TE is set to 1, the
ASCI receiver is enabled. When TE is reset to 0, the trans-
mitter is disabled and any transmit operation in progress is
interrupted. However, the TDRE flag is not reset and the
previous contents of TDRE are held. TE is cleared to 0 in
IOSTOP mode during RESET.
RTS0: Request to Send Channel 0 (bit 4 in CNTLA0
only). If bit 4 of the System Configuration Register is 0, the
RTS0/TxS pin has the RTS0 function. RTS0 allows the
ASCI to control (start/stop) another communication devic-
es transmission (for example, by connecting to that de-
vice’s CTS input). RTS0 is essentially a 1 bit output port,
having no side effects on other ASCI registers or flags.
Bit 4 in CNTLA1 is used.
CKA1D = 1, CKA1/TEND₀ pin = TEND₀
CKA1D = 0, CKA1/TEND₀ pin = CKA1
Cleared to 0 on reset.
MPBR/EFR: Multiprocessor Bit Receive/Error Flag Re-
set (bit 3). When multiprocessor mode is enabled (MP in
CNTLB = 1), MPBR, when read, contains the value of the
MPB bit for the last receive operation. When written to 0,
the EFR function is selected to reset all error flags (OVRN,
FE, PE and BRK in the ASEXT Register) to 0. MPBR/EFR
is undefined during RESET.
DS971800401
PRELIMINARY
1-39