Z8S18020FSC Datasheet, PDF (49/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
CLOCK MULTIPLIER REGISTER (Z180 MPU ADDRESS 1EH)
76
00
54
11
32
11
10
11
RESERVED
LOW NOISE CRYSTAL
Bit 6. Low Noise Crystal Option. Setting this bit to 1 will
1 ^{enable the low noise option for the EXTAL and XTAL pins.}
This option reduces the gain, in addition to reduction the
output drive capability to 30% of its original drive capability.
The Low Noise Crystal Option is recommended in the use
of crystals for PCMCIA applications where the crystal may
be driven too hard by the oscillator. Setting this bit to 0 will
select for normal operation of the EXTAL and XTAL pins.
The default for this bit is 0.
X2 CLOCK MULTIPLIER
Figure 54. Clock Multiplier Register
Bit 7. X2 Clock Multiplier Mode. When this bit is set to 1,
this allows the programmer to double the internal clock
from that of the external clock. This feature will only oper-
ated effectively with frequencies of 10-16 MHz (20-32MHz
internal). When this bit is set to 0, the
Z80180/Z8S180/Z8L180 device will operate in normal
mode. Upon powerup, this feature is disabled.
Note: Operating restrictions for device operation are listed
below. If low noise option is required, and normal device
operation is needed, use the clock multiplier feature.
Table 9. Low Noise Option
Low Noise
ADDR 1E, bit 6=1
20 MHz @ 4.5V, 100°C
10 MHz @ 3.0V, 100°C
Normal
ADDR 1E, bit 6=0
33 MHz @ 4.5V, 100°C
20 MHz @ 3.0V, 100°C
DS971800401
PRELIMINARY
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