Z8S18020FSC Datasheet, PDF(19/70 Page) Zilog, Inc.

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Z8S18020FSC Datasheet, PDF (19/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

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Zilog

Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

Figure 15 shows the timing for exiting IDLE mode due to Z80180/Z8S180/Z8L180 takes about 9.5 clocks to restart.

an interrupt request. Note that the

IDLE Mode

Opcode Fetch or Interrupt

Acknowledge Cycle

9.5 Cycle Delay from INTi Asserted

NMI

INTi

A19-A0

HALT

FFFFFH

Figure 15. Z80180/Z8S180/Z8L180 IDLE Mode Exit due to External Interrupt

While the Z80180/Z8S180/Z8L180 is in IDLE mode, it will

grant the bus to an external master if the BREXT bit

(CCR5) is 1. Figure 16 shows the timing for this sequence.

Note that the part takes 8 clock cycles longer to respond to

the Bus Request than in normal operation.

After the external master negates the Bus Request, the

Z80180/Z8S180/Z8L180 disables the PHI clock and re-

mains in IDLE mode.

DS971800401

PRELIMINARY

1-19

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