MDS213 Datasheet, PDF (98/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
18.2.11.9 CPUIRDAT - CPU INTERNAL RAM DATA REGISTER
The 3 data registers are used when CPU reads or writes the content of the specified entry. table
• CPUIRDAT0
Address: h588
CPU Internal RAM Data register for Data[31:0]
• CPUIRDAT1
Address: h58C
CPU Internal RAM Data register for Data[63:32]
• CPUIRDAT2
Address: h590
CPU Internal RAM Data register for Data[95:64]
Access: Non-Zero-Wait-State,
Direct Access,
Write/Read
31
0
CPIRDAT0
CPIRDAT1
CPIRDAT2
Data[31:0]
Data[63:32]
Data[95:64]
The content is dependent as to the type of table, as describe follows.
Type = MC ID (6bits)
31
65
0
CPIRDAT0
MCID[5:0]
Bit [5:0] MCID
multicast ID FIFO data output
(Note that up to 16 for this version.)
Bit [31:6] Reserved
Type = VMAP Table (27 bits)
31
27 26 25
13 12
0
CPIRDAT0
RE
VLAN TAG Enable [12:0]
VLAN Port Enable [12:0]
Bit [12:0] VLAN Port Enable [12:0]
Bit [25:13] VLAN Tag Enable [12:0]
Bit [26] RE
Bit [31:27] Reserved
one bit for each Ethernet MAC Port
Identify the ports associated with each VLAN
0 = disable 1 = enable
one bit for each Ethernet MAC Port
0 = disable 1 = enable
Remote Ports Enable: Indicate some members in the remote
device.
0=disable1=enable
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Zarlink Semiconductor Inc.