MDS213 Datasheet, PDF (31/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
63
FDB block
must start from 0
0
0
FDB
Frame Data Buffers
(1.5KB x # of frame buffers)
Transmission queues
(4x13 =52 queues)
(each entry = 1DW)
(#entry of Queue = 128 to 1K)
CPU/HISC Mailing List
(#entry = 128 to 1K)
(each mail entry=32 bytes
to 64 bytes)
VLAN Table
(4k entry, 8B/entry)
VLAN MAC Table
(2k entry)
(each entry=256, 128 or 64 bit)
Byte Byte Byte ByteByte ByteByte Byte
765 4321 0
Programmable Size
Programmable Size
32KB
16, 32 or 64KB
MAX
1/2MB, 1MB or 2MB
Figure 5 - Memory Map of Managed System
5.2.2 Frame Data Buffers
The Frame Data Buffers (FDBs) accommodates the incoming data frames and partitions them into data blocks,
where each block occupies 1.5K bytes. The number of data blocks in FDB are configured by setting the value in the
register FCBSL[9:0]. Since MDS213 supports up to 2M Bytes memory, the maximum number of data blocks is 1K.
Note: The FDB must start at location 0.
5.2.3 Transmission Queues
The Transmission Queue controls the scheduling of the transmission ports, where each of these ports can support
up to 4 priorities for each of the 13 ports of the MDS213. The number of priorities is programmable. Thus, the
MDS213 may be configured for 13, 26, 39 or 52 Transmission Queues and may support 1, 2, 3 or 4 priority levels,
respectively. The size of the Transmission Queue is 128, 256, 512, or 1024 entries and may be setup during the
initialization phase.
The Search Engine maintains the contents of each queue, where each queue consists of transmission priorities.
Each double word (4-bytes) entry contains a FDB handle, which points to the corresponding frame in the buffer.
5.2.4 Mailing List
The Mailing List provides a communication channel between the HISC and CPU in managed mode. The size of a
mail entry varies, ranging from 32 to 64 bytes, which is determined by the initialization setup. When the CPU or the
HISC writes mail, the CPU/HISC can obtain a free mail by the register AFML that contains the addresses of free
mail. Conversely, when the CPU or HISC reads its mail, the CPU/HISC accesses the mail by the register AMBX
that contains the address of a CPU/HISC mail. All of the mail registers are maintained by the hardware.
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