MDS213 Datasheet, PDF (41/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
• It provides independent 2 bit wide (di-bit) transmit and receive data paths
• It uses TTL signal levels, compatible with common digital CMOS ASIC processes.
Data Sheet
RMII Specification Signals
Signal Name
REF_CLK
M[0:11]_CRS_DV
M[0:11]_RXD[1:0]
M[0:11]_TX_EN
M[0:11]_TXD[1:0]
M[0:11]_RX_ER
Direction
(with respect of the PHY)
Input or Output
Input
Input
Output
Output
Input (Not required)
Direction
(with respect to the MAC)
Synchronous clock reference for
receive,
transmit and control interface
Carrier Sense/Receive Data Valid
Receive Data
Transmit Enable
Transmit Data
Receive Error
Table 5 - RMII Specification Signals
9.2 The Gigabit Media Independent Interface (GMII)
The GMII supports the 1000Mbps full-duplex operations of the MDS213, based on the Media Independent Interface
(MII) defined by IEEE Std 802.3 (Clause 22). The GMII retains the names and functions of most of the MII signals,
but defines valid signal combinations for 1000Mbps operations. The GMII transfers data in each direction for the
Data [7:0], Delimiter, Error, and Clock signals. The GMII implementation extends the Transmit Data (TXD) and
Receive Data (RXD) signals of the MII from four bits wide to eight bits wide and synchronizes the data and the
delimiters using a Gigabit Transmit Clock (GTX_CLK) instead of the MIIs' Transmit Clock (TX_CLK).
9.2.1 The MII Management Interface
The GMII uses the MII Management Interface is used to control and gather status information from the Gigabit
Physical Layer (PHY) to configure MDS213 operations using Auto-negotiation. The management interface consists
of a pair of signals, called the M_MDIO and M_MDC management pins.
9.2.2 MII Command and Status Registers
The MDS213 utilizes the MII Command and Status registers defined in the 10/100Mbps Specification and additional
extended registers to support Auto-negotiation (IEEE Std 802.3, Clause 37). The commonality of the MII
management registers will allow the MDS213 to determine the capabilities supported by the PHY and to implement
such functions as "Start of Frame" and "Determine PHY Address."
9.3 The Physical Coding Sublayer with Ten Bit Interface (TBI):
Zarlink MDS213 includes the Physical Coding Sublayer (PCS) block. It performs 8B/10B conversion between GMII
and Ten Bit Interface (TBI). The Collision Detect (COL) and Carry Sense (CRS) signals are generated from PCS to
GMII internally when using TBI interface PHY. The PCS block also includes an Auto Negotiation function. The PCS
block can be disabled by using the Device Configuration Register (DCR2) when GMII interface PHY is used.
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Zarlink Semiconductor Inc.