MDS213 Datasheet, PDF (74/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
Bit [24] MCT
Search Engine found looped MCT Chain.
Bit [31:25] Reserved
Note: MAIL_ARR, CPU_Q_Out and interrupts cannot be cleared by the CPU. They will be cleared whenever their
queues are emptied.
18.2.3 Buffer Memory interface register
18.2.3.1 MWARS - Memory Write Address Register - Single Cycle
Access: Zero-Wait-State,
via FIFO,
Write
Address: h780
31
28 27 26 _{24 23 22 21 20}
BE[3:0]
00001 _I/E
Address MA[20:3]
321 0
SP LK
Bit [0]
Bit [1]
Bit [20:2]
Bit [21]
Bit [22]
LK
SP
MA [20:2]
Reserved
I/E
Bit [27:23] Count
Bit [31:28] BE [3:0]
Lock Flag (for internal memory only)LK=0 UnlockLK=1 Lock
Swap Byte Order
Buffer memory address Bit [20:2] - (Bit [1:0] = 00)
Indicates the Address is Internal or External memory
I/E=0 Internal memory
I/E=1 External memory
Must be 00001
Byte lane enables
CPU Bus Type
Little Endian
Big Endian
Bit [31]
BE [3]
BE [0]
Bit [30]
BE [2]
BE [1]
Bit [29]
BE [1]
BE [2]
Bit [28]
BE [0]
BE [3]
18.2.3.2 MRARS - Memory Read Address Register - Single Cycle
Access: Zero-Wait-State,
via FIFO,
Write
Address: h784
31
28 27
24 23 22 21 20
BE[3:0]
00001 _I/E
Address MA[20:2]
321 0
SP LK
Bit [0]
LK
Bit [1]
Bit [20:2]
Bit [21]
Bit [22]
SP
MA [20:2]
Reserved
I/E
Lock Flag memory
LK=0 Unlock
Swap Byte Order
Buffer memory address Bit [20:2] -
LK=1 Lock
(Bit [1:0] = 00)
Indicate the Address is Internal or External memory
I/E=0 Internal memory
I/E=1 External memory
74
Zarlink Semiconductor Inc.