MDS213 Datasheet, PDF (87/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
Bit [22:18]
Bit [17:16]
Bit [15:0]
REG_AD
TA
DATA
5-bit Register Address in PHY
Turnaround - "10" for write
16-bit Write Data to PHY
18.2.9.2 AMIIS - MII Status Register
The upper layer services should read this register for data sent by the PHYs. The lower 16 bits contain data
received by the Management Module
Access: Non-Zero-Wait-State,
Direct Access, Read only
Address:
h658
31 30 29
RY VD
16 15
DATA (16-bit)
210
Bit [31]
Bit [30]
Bit [15:0]
RDY
VALID
DATA
Data Ready
Data Valid
16-bit Read Data from PHY
Bit [31]
RDY
1
1
0
Bit [30]
VALID
1
0
X
Description
Data field contains valid data from the PHYs
Data field contains invalid data from the PHYs
Data field is not ready to be read by Switch Manager CPU
18.2.10 Flow Control Management
18.2.10.1 AFCRIA - Flow Control RAM Input Address
Access: Non-Zero-Wait-State,
Direct Access, Write only
Address: h65C
31
32
0
address
Bit [2:0] 3-bit address for the RAM in MAC storing flow control frame
Usage: Flow Control Frame consists of 64 Bytes. Using AFCRIA and AFCRID0-1, the CPU loads 8 bytes each
time. The CPU specifies the address in AFCRIA and writes the content of 4 bytes in AFCRID0 and 4 Bytes in
AFCRID1. Then repeats the above procedure 8 times to load a whole flow control frame into the Chip.
87
Zarlink Semiconductor Inc.