MDS213 Datasheet, PDF (96/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
18.2.11.5 IPMCMSK- IP Multicast MAC Address Mask
The 6-byte of IP multicast MAC Mask is stored in two 32-bit registers
• IPMCAS0 IP Multicast MAC Mask Byte [3:0]
Address:h5F0
• IPMCAS1 IP Multicast MAC Mask Byte [5:4]
Address:h5F4
Access: Non-Zero-Wait-State,Direct Access,Write/Read
31
IPMCMSK0
MASK 3
24 23
MASK 2
16 15
IPMCMSK1
11
87
MASK 1
MASK 5
0
MASK 0
MASK 4
These two registers define the MAC Mask of IP multicast.
Default = h"ff:ff:ff:80:00:00".
18.2.11.6 CFCBHDL - FCB Handle Register For CPU Read
Access: Non-Zero-Wait-State, Direct Access,
Read only
Address: h580
Usage: When CPU requests a free FDB to write a frame, it must request a free FCB via this register. The register
contains a free handle of FCB, which also pointer to a free FDB.
CPU reads FCB Handle: (When the CPU write FDB, it requires a FDB handle first).
CPU checks CFCBHDL[31],H_RDY ready or not. If so, CPU gets the FCB Handle from CFCBHDL[9:0]
31
10 9
0
H_R
DY
FCB_Handle[9:0]
Bit [9:0] FCB_HANDLE
Bit [30:10] Reserved
Bit [31] H_RDY
FCB Handle Address
FCB Handle Ready
0=Not Ready
1=Ready
18.2.11.7 CPU Access Internal RAMs (Tables)
Usage: (refer to section 9 for detail).
The CPU uses the following methods to access the five internal RAMs, including MCID, VLAN port mapping
(VMAP), BM control Table (BMCT), FCB and Transmission Queue control (QCNT).
Registers:
• CPUIRCMD: Command register
• CPUIRDAT0: Data Register for specific entry of content Bit[31:0]
• CPUIRDAT1: Data Register for specific entry of content Bit[63:32]
• CPUIRDAT2: Data Register for specific entry of content Bit[95 64]
• CPUIRRDY: Data Read Ready.
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