MDS213 Datasheet, PDF (45/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
MDS213
Primary
Bus
Request
Master
state
Machine _Bus
Arbiter
Grant _{Chip select}
CPU
Only for Debug
P_GNTC
P_REQC
P_REQ1
P_GNT1
P_CS
MDS213
Secondary
Master
state
Machine
Figure 14 - Block Diagram of the Arbiter
Note: In unmanaged mode, the CPU is used only for debugging purposes and cannot be involved in switching
decisions or management activities.
During Power On/Reset, the bootstrap pin, BS_PSD, determines which device will be the primary and activates the
arbiter of that device. At most, three devices, two MDS213 devices and one CPU, can operate on the CPU
Interface at the same time.
Each device may request access to the CPU Interface by sending a Request signal to the arbiter. The arbiter, then
sends a Grant signal acknowledging which device has been chosen.
An arbitrate scheduler, located within the arbiter, decides which device functions as the Master device. If the Master
is the secondary device, the arbiter will send a Grant signal and a Chip Select (P_CS) signal to the device. If the
Master is the primary device, the Grant signal is sent directly to the Master State Machine (MSM) by an internal
signal. The scheduler then performs a round robin configuration and allows each device to be the Master device.
Note: During Power On/Reset, the arbiter always selects the primary device to be master device.
10.4 CPU Interface in managed mode
The CPU Slave State Machine (SSM) accepts Address Strobe (P_ADS#), Chip Select (P_CS#), and Bus-Data
Ready (P_RDY#) signals as ready state signals of a CPU cycle.
10.4.1 CPU Access
The 32-bit CPU bus interface supports both Big and Little Endian CPUs. The difference between Big and Little
Endian is the byte swapping when CPU writes data to external memory. Table 15 summarizes the byte swapping
operation and Figure 15 illustrates an example of bytes swapping.
If using Little Endian
If using Big Endian
Bit[1] must be ’0’ for register of
MWARS, MRARS, MWARB, MRARB
Bit[1] must be ’1’ for register of
MWARS, MRARS, MWARB, MRARB
No byte swapping for CPU data write in or
read out to/from MWDR, MRDR registers.
Automatic Byte swapping for CPU data write
in or read out to/from MWDR, MRDR
registers.
Figure 15 - Little and Big Endian Byte Swapping Operation
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