MDS213 Datasheet, PDF (28/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
As a frame lives through its lifecycle, its status is updated in the FCB. The FCB also contains vital frame
information, such as destination port and length. There is a one-to-one correspondence between the FCB and the
FDB: FCB#274 contains information about the frame stored in FDB#274. An FCB/FDB pair is called a "frame
buffer," or simply a "buffer." The number 274 is called the handle or the buffer handle. The Frame Engine takes care
of the distribution and the releasing of buffers. It also keeps buffer counters to ensure no port or single type of traffic
occupies too many buffers.
The receiving DMA (RxDMA) moves frame data from the MAC RxFIFO to the FDB. Before the RxDMA writes frame
data into the FDB, it must obtain a free buffer handle from the buffer manager. A free buffer handle points to an
empty or released frame buffer, ensuring that no stored frame data will get overwritten. After the EOF has been
safely stored in the FDB, it writes the frame information to the FCB and issues a switching request to the Search
Engine. If the frame is found to be bad (e.g., bad CRC), the buffer handle will be released and nothing will be written
to the Search Engine or the FCB. This returns the buffer back to circulation and the frame is discarded.
The RxDMA can fail to obtain a free buffer handle for two reasons. All buffers are currently occupied, or the
received frame is a multicast frame and the multicast buffer quota is exhausted. In either case, the RxDMA will
discard the frame, without getting a handle. If set, the register bit DCR2[26], IPMC, enables IP multicast privileges.
If enabled, the RxDMA discards regular multicast frames if the multicast forwarding FIFOs occupancy exceeds the
programmable threshold (see register MBCR[21:20], MCTH). An IP multicast frame is discarded only when the
multicast frame's forwarding FIFO is full.
4.1 Transmission scheduling
There are four transmit scheduling queues (TxQ) per port, one for each priority. When a port is ready to transmit,
when the previous frame finished transmitting, the port control module notifies the Frame Engine. The Frame
Engine selects one TxQ out of the four priority queues, depending on the frame's arrival time and weighted round
robin state (refer to the QoS chapter for more detail). It reads an entry from the selected transmission scheduling
queue, and if the source port of the selected frame is local, a transmission request is issued to the local TxDMA
module. If, on the other hand, the source port is remote, the data request message is forwarded across the XPipe
and subsequently arrives at the forwarding engine.
The four transmit scheduling queues per output port allows the Frame Engine to perform weighted round robin
(WRR) to provide quality of service (QoS). The Search Engine classifies the frames into four internal priorities, Q0,
Q1, Q2, and Q3, in decreasing priority. The 802.1p priority bits are mapped to the internal priorities by a
programmable mapping, accessible via register AVTC. The user can program the queue weights via register AXSC,
and thereby control the relative rates of the four internal-priority tagged frames.
The maximum TxQ lengths are programmable from 128 entries to 1024 entries per queue. 52 TxQs are located in
the external memory. The maximum queue lengths and the base memory addresses are accessible by the register
group {CPUIRCMD, CPUIRDAT, CPUIRRDY}, under type QCNT.
4.2 Buffer Management
The buffer manager is responsible for the free handle allocation, buffer usage monitoring, buffer release and FCB
access control. Free handles point to buffers that are not occupied by a frame. These free buffers can be allocated
to a new frame received by the RxDMA. When the Frame Engine is done processing a frame, its handle is released
to the free handle pool.
The free handle pool must be initialized via the register group CPUIRCMD, CPUIRDAT, CPUIRRDY, type BMCT,
before device operation. The Buffer Manager Control Table (BMCT) is the pool of free handles. At reset, the BMCT
is empty. Prior to device operation, free handles must be written to the BMCT. The user must write the integers
{0,1,2,3, … K-1} to the BMCT one-at-a-time, where K is the maximum number of buffers. The value of K depends
on the external memory size and partition, and it can be 128, 256, 512, or 1024.
If all buffers are used, no more frames can enter the device. The Frame Engine keeps buffer counters that limit the
number of buffers occupied by frames destined for each output port. If a buffer counter exceeds a programmable
28
Zarlink Semiconductor Inc.