MDS213 Datasheet, PDF (80/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
18.2.5.2 COTQ - CPU Output Queue
Access: Non-Zero-Wait-State,
Direct Access, Read only
Address: h70C
31 30
CPU Output Queue Entry
Data Sheet
0
Bit [30:0] 31-bit CPU Output Queue Entry
Bit [31] Status queue is ready
18.2.6 Switching Control register
18.2.6.1 HPCR - HISC Processor Control Register
Access: Non-Zero-Wait-State,
Direct Access, Write/Read
Address: h6C0
31
321 0
RS LD HT
Bit [0]
Bit [1]
Bit [2]
Bit [31:3]
HT
Halt the HISC processor from execution Not Apply for non-managed
mode (It can be fixed in next cut.)Power-up default = 1
LD
Switch the Micro-Code Memory from instruction fetch mode to down-
loading mode
RS
Reset IP to 0 - (Write only bit)
(This bit is auto reset to 0 after IP is reset to 0)
Reserved
RS LD HT
101
001
01X
100
000
11X
State
INIT
HALT
LOAD
START
EXEC
--
Description
Initialization State: -- Stopped HISC execution, reset IP to 0.
Halt State: -- Stopped HISC execution, waiting for HT=0.
Micro-Code Loading State: -- Stopped HISC execution, increment IP for
every Wr/Rd to HMPC
Start State: -- Reset IP=0, and start HISC execution.
Execution State: -- Continue HISC execution without reset IP.
Illegal State.
80
Zarlink Semiconductor Inc.