MDS213 Datasheet, PDF (100/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
18.2.11.10 CPUIRRDY - Internal Ram Read Ready For CPU
Access: Non-Zero-Wait-State, Direct Access, Write/Read
Address: h594
The Frame Engine sets this ready bit to notify the CPU that the requested data is ready to read.
31
Data Sheet
10
RD
Y
Bit [0]
R_RDY
Bit [31:1] Reserved
Data in Data registers is ready for CPU Read
18.2.11.11 LEDR- LED Register
Access: Non-Zero-Wait-State,
Direct Access,
Write/Read
Address: h598
31 30
28 27 26 25 24 23
16 15
87
0
SS
LCK HT
UDEF3
UDEF2
UDEF1
Bit [7:0] UDEF1 User defined information status 1 for debug purpose
Bit [15:8] UDEF2 User defined information status 2 for debug purpose
Bit [23:16] UDEF3 User defined information status 3 for debug purpose
Bit [25:24] HT
Holding time for LED signal (Default=00)
00=8msec
01=16msec
10=32msec
11=64msec
Bit [27:26] LCLK
LED Clock frequency (Default=00)
00= 100M/8=12.5Mhz
01= 100M/16=6.25Mhz
10= 100M/32=3.125Mhz
11= 100M/64-1.5625Mhz
Bit [30:28] Reserve
Bit [31] SS
Start Shift the status bits out from the master device.
This bit has no effect on the slave chip.
Note: UDEF1-UDEF3 are used for debug purpose. The contents of UDEF1-3 are loaded by CPU and the usage of
these are up to software.
18.2.12 Ethernet MAC Port Control Registers
One set for each Ethernet MAC Port [12:0]
MII related controls applies to Port [1:0] only
Port 12 is always dedicated to GMAC
100
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