MDS213 Datasheet, PDF (72/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
18.2.1.5 DCR3 - Interfaces Status Register
Access: Zero-Wait-State,
Direct Access, Read only
Address: h7CC
31
25 24
21 20
16 15
12 11
87
43210
Que_Stat
Mem_Stat
Bit [3:0]
Bit [7:4]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Reserved
Mem_Stat
BB
RE
WE
Res.
Buffer Memory Interface Status
Buffer Memory Busy, CPU interface is busy accessing Memory
Read FIFO Empty, the FIFO that CPU interface reads is empty
Write FIFO Empty, the FIFO that CPU writes is empty
Reserved
Bit [11:8] Que_Stat
Bit [8]
IQ_Rdy
Bit [9]
IQ_Full
Bit [11:10] Reserved
Bit [31:12] Reserved
Queue Manager Interface Status
CPU Input Queue is ready for CPU to write into queue
CPU Input Queue is full
18.2.1.6 MEMP - Memory Packed Register
Access: Non-Zero-Wait-State, Direct Access, Write/Read
Address: h7DC
31 - 30
17 16 15
87
NP
WCL
5
0
RCL
Bit [7:0]
Bit [15:8]
Bit [16]
Bit [31:17]
RCL
WCL
NP
Read Cycle Limit (Unit is system Clock).
Threshold of reads cycle time.
Write Cycle Limit (Unit is system Clock).
Threshold of writes cycle time.
Not Packed
NP=0 Enable the feature of memory read/write
packed.
Reserved
Default=16
Default=16
Default=0
NP=1 Disable, memory
access will be a pure
round-robin scheme.
72
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