MDS213 Datasheet, PDF (97/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
CPU Reads FCB
• CPU write the read command into CPUIRCMD with FCB Handle, W/R=0. And set C_RDY. Also, set the
table type = FCB, (CPUIRCMD[14]=1)
• Frame Engine puts the specified FCB content into CPUIRDATL and CPUIRDATM
• Frame Engine Clear C_RDY
• Frame Engine set CPUIRRDY[0] to notify CPU that the FCB data is ready to be read.
CPU writes FCB
• CPU writes the content of FCB into CPUIRDATL and CPUIRDATM
• CPU writes the handle of FCB into CPUIRCMD [9:0], set CPUIRCMD [10] = 1,(write CMD), set
CPUIRCMD[31]=1, CMD_RDY and set the Table Index to FCB, (CPUIRCMD[14]=1).
• Frame Engine clears CPUIRCMD [31], C_RDY, when Frame Engine reads FCB done
• Apply the similar method to access the other four tables.
18.2.11.8 CPUIRCMD - CPU Internal RAM Command Register
Access: Non-Zero-Wait-State,
Direct Access,
Write/Read
Address: h584
Command for CPU accesses five internal Tables
31 30
C_R
DY
16 15 14 13 12 11 10 9
QC FC BM VM MC _W/
NT B CT _{AP ID R}
0
Entry Index [9:0]
Bit [9:0]
Bit [10]
Entry Index
Type = MCID(16)
Type = VMAP(256)
Type = BMCT(1K)
Type = FCB(1K)
Type = QCNT (64)
W/R
Bit[15:11] Table bit map
Bit[11]
MCID
Bit[12]
VMAP
Bit[13]
BMCT
Bit[14]
FCB
Bit[15] QCNT
Bit [30:16] Reserve
Bit [31] C_RDY
The index of specified entry
Entry index[3:0]
Entry index[7:0]
Entry index[9:0]
Entry index[9:0]
Entry index[5:0]
Write or Read the table entry
0=Read
1=Write
Bit maps of five tables.
MCID=1 Use MC ID l Table
VMAP=1 Use VLAN port mapping Table (VMAP)
BMCT=1 Use Buffer Manager Control Table (BM control)
FCB=1 Use FCB Table
QCNT=1 Use Transmission Queue control Table (QM control)
Command Ready
0=Not Ready
1=Ready
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