MDS213 Datasheet, PDF (103/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
Default =0 - Disable
Bit [12] Ext_Lpback
Setting this bit indicate an external loop-back
(connection of TXCLK, TXD[0:3] to RXCLK, RXD[0:3]
are required)
Default =0 -- Disable
Bit [13] FC_Enable
Flow Control EnableDefault =0 - Disable
When enabled:
• In Half Duplex mode, the MAC Transmitter applies back pressure for flow control.
• In Full Duplex mode, the MAC Transmitter sends Flow-Control frames when necessary. The MAC Receiver
interprets and processes incoming Flow Control frames. The MAC Receiver marks all Flow Control Frames.
Receive DMA discards the received Flow Control Frame and send status reports to the Switch Manager for
statistic collection.
When Disabled:
• The MAC Transmitter does not asserts flow control by sending Flow Control frames nor jamming collision.
• The MAC Receiver still interprets and processes the Flow-Control frames. The MAC Receiver marks all
Flow Control frames. Receive DMA discards the received Flow Control frames and send a status report to
the Switch Manager for statistic collection.
Bit [14] Link_Polarity
Bit [15] Tx_Enable
Bit [16] Reserved
Bit [23:17] IFG
Bit [31:24] Reserved
Selects the input polarity of Link Status signal
0 = Low true (Default) 1 = High true
Enables MAC Transmitter for transmission
Default =0 - Disable
Inter-frame Gap (Default=7'd24)
Use to adjust the inter-frame gap. (Unit =transmit Clock.)
The default is 7'd24, stands for 24 transmit clock (each clock
transmit 4 bits).
18.2.12.3 ECR2 - MAC Port Interrupt Mask Register
Access: Non-Zero-Wait-State,
Direct Access,
Address: h0x2*4
x: port number
h008
ECR2_p0
h048
ECR2_p1
h088
ECR2_p2
h0c8
ECR2_p3
h108
ECR2_p4
Write/Read
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Zarlink Semiconductor Inc.