MDS213 Datasheet, PDF (73/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
18.2.2 Interrupt Control Registers
Four 32-bit Control Registers.
ISR Interrupt Status RegisterIdentify the unmasked interrupt request sources
Access: Zero-Wait-State,
Direct Access,
Read only
Address: h7E0
ISRM Masked Interrupt Status Reg.Identify the sources of interrupt with masking
• Access: Zero-Wait-State,
Direct Access,
Read only
• Address: h7E4
Data Sheet
IMSK Interrupt Mask RegisterDefines the interrupt sources to be masked
• Access: Non-Zero-Wait-State,
Direct Access,
Write/Read
• Set bits to 1 to mask the corresponding interrupt sources
• Address: h7E8
IAR Interrupt Acknowledgment Reg.Clear the interrupt request bits
• s Access: Non-Zero-Wait-State,
Direct Access,
• s Set bits to 1 to clear the corresponding interrupt sources
• s Address: h7EC
All 4 registers have a common register format and bit assignment
Write only
31
25 24 23
11 10 9 8 7 6 5 4 3 2 1 0
MC
T
MAC_Port Interrupt
FM HI MA
L _{SC IL}
BPFC DBBS CP
IL R R Q
Interrupt MAC port mapping bit/port
Interrupt Source
Interrupt Sources (The following bits need to be redefined.)
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit [10]
CPU_Q_Out
BSR
Double R
FCB_Low
HISC_BP
Reserved
Reserved
MAIL_ARR
HISC_TO
Reserved
FML_Av
Bit [23:11] MAC_PORT
CPU output queue level interrupt
Bad switch response
Double Release
FCB Low
HISC instruction pointer matched with Breakpoint Register
Mail arrived from HISC
HISC Timeout Interrupt
Link manager informs CPU that at least 16 Free Mail entry available
after CPU encounters empty Free Mail list situation.
Interrupt from MAC ports
Bit [11] for Port 0, Bit [12] for Port 1 … Bit [23] for port 12, port 12 is a
Giga port
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