MDS213 Datasheet, PDF (29/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
threshold, its associated output port is "blacklisted." Entering frames destined to this output port are discarded, until
the counter goes below the threshold. This threshold is programmed via registers BCT and BCHL. These counters
prevent complete depletion of buffers due to an overloaded port, thus allow frames destined for non-congested
ports to enter the system. This effectively avoids head-of-line blocking.
The Frame Engine also keeps a buffer counter for multicast traffic types. The buffers occupied by incoming
multicast frames are limited. This prevents multicast frames from blocking unicast ones from entering the system.
The threshold for multicast traffic types is programmed via register MBCR.
5.0 Frame Buffer Memory
5.1 Frame Buffer Memory configuration
The MDS213 system utilizes external SRAM for its Frame Buffer Memory configuration, where the size of memory
supported is ½ MB, 1MB and 2MB configurations. The following table shows four memory configuration examples
for the MDS213 system.
SRAM Type
One Bank
Two Bank
Address
Size
Address
Size
64Kx32
L_A[18:3]
½MB
L_A[19:3]
1M
128Kx32
L_A[19:3]
1MB
L_A[20:3]
2M
Table 1 - Type and Size of Memory Chips
The following figure shows the connections between the Frame Buffer Memory and the MDS213 for one-bank and
two-bank memory configurations.
SRAM ^L_D[31:0]
64Kx32
L_A[18:3]
MDS213
SRAM ^L_D[63:32]
64Kx32
One Bank 0.5M
64Kx32
SRAM L_D[31:0]
128Kx32
L_A[19:3]
MDS213
SRAM L_D[63:32]
128Kx32
One Bank 1.5M
128Kx32
6S4RKAxM362S4RKxA3M2
L_D[31:0]
L_D[31:0]
CE _{L_A[18:3]}
CE
MDS213
L_A[19]
6S4RKAxM362S4RKAx3M2
L_D[63:32]
L_D[63:32]
Two Bank 1M
64Kx32
SRAM6S4RKxA3M2
128Kx32
L_D[31:0]
L_D[31:0]
CE _{L_A[19:3]}
CE
MDS213
L_A[20]
12S8RKAx3M62S4RKAx3M2
L_D[63:32]
L_D[63:32]
Two Bank 1M
128Kx32
Figure 4 - Frame Buffer Memory Configuration
29
Zarlink Semiconductor Inc.