MDS213 Datasheet, PDF (44/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
10.1.6 Interrupt Request
The CPU Interface accepts an Interrupt Request (IRQ) from each device connected to the interface, and supports
centralized interrupt arbitration and vector response. The interrupt output is an open-drain option with
programmable polarity.
10.2 Control Bus Cycle Waveforms
P_CLK
P_ADS#
P_RDY#
one-wait
state
P_A[10:1]
P_D[31;0]
P_BRDY#
P_BLAST#
Write Cycle
Read Cycle
Burst
Sample
wait
wait Read
wait
Read Read Read Read
Read Cycle = 8 clks
Figure 13 - Control Bus I/O
10.3 The CPU Interface in Unmanaged Mode
In unmanaged mode, the HISC processor of the Master device communicates with the slave device as a CPU
function. Three registers and one flag are used to communicate between the HISC processor and the CPU
Interface.
10.3.1 Arbiter
The arbiter of the XpressFlow MDS213 is an internal logic device used to determine which device will function as
the master device. The connections between the master device, slave device, and the CPU are used for debugging
purposes only. See Figure 14.
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