MDS213 Datasheet, PDF (68/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
Tag
Description
Address
W/R
CPUIRDAT1 CPU Internal RAM Data Register - 1
58C
W/R
CPUIRDAT2 CPU Internal RAM Data Register - 2
590
W/R
CPUIRRDY Internal RAM Read Ready for CPU
594
--/R
LEDR
LED Register
598
W/R
10. Ethernet MAC Port Control Registers - (substitute [N] with Port Number, N = {0..12})
ECR0
MAC Port Control Register
[N*4]0
W/R
ECR1
MAC Port Configuration Register
[N*4]4
W/R
ECR2
MAC Port Interrupt Mask Register
[N*4]8
W/R
ECR3
MAC Port Interrupt Status Register
[N*4]C
--/R
ECR4
Status Counter Wrap Signal
[N*4+1]0
--/R
PVIDR
PVID Register
[N*4+2]4
W/R
Table 8 - MDS212 Register Map (continued)
18.2 Register definitions
18.2.1 Device Configuration Register
18.2.1.1 GCR - Global Control Register
Access: Zero-Wait-State, Direct Access, Write only
Address: h7C0
31 24 23
20 19
16 15
12 11
87
432
0
SYN
Op-Code
Bit [2:0] Op-Code
3-bit Operation Control Code
Op-Code Command
Description
000
Clr RST Clear Device Reset: - Allows state machines to exit from RESET state
and to initialize their internal control parameters if necessary.
001
RESET Device Reset: -- Resets all internal state machines of each device and
stays in RESET state (except the Processor Bus Interface logic).
010
EXEC Execution: -- Allows state machines to start their normal operations.
011
--
No-Op
1XX
--
No-Op
Table 9 - Global Control Register
Bit [7:4] SYN bits, reserved for HISC Usage.
68
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