MDS213 Datasheet, PDF (76/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
18.2.3.4 Memory Read/Write Data Registers
Four 32-bit data registers share a common format
• MWDR Memory Write Data Register
• Access: Zero-Wait-State, via FIFO,
Write only
• Address: h790
• MRDR Memory Read Data Register
• Access: Zero-Wait-State, Direct Access, Read only
• Address: h794
Data Sheet
Byte Order depends on CPU types
• Little Endian CPUs
31
24 23
16 15
87
Byte [3]
Byte [2]
Byte [1]
• Big Endian CPUs
31
24 23
16 15
87
Byte [0]
Byte [1]
Byte [2]
0
Byte [0]
0
Byte [3]
18.2.3.5 VTBP - VLAN ID Table Base Pointer
Access: Non-Zero-Wait-State,
Direct Access,
Address:h798
Write/Read
31
17 16 15
11 10 9 8 7 6 5
0
VMACB
VLMS VLAN ID BASE
Bit [5:0]
VIDB
Bit [6]
Bit [8:7]
Reserved
VLMS
Bit [15:9]
VMACB
Bit [31:16] Reserved
VLAN ID Table Base, serves as [20:15] bits of address.
(VLAN ID Table is 32KB)
The size of VLAN MAC Table Default=11
00= reserved
01=16K (for 64 VLANs)
10=32K (for 128 VLANs)11=64K (for 256 VLANs)
VLAN MAC Table Base, serves as [20:14] bit of address.
This table indicates the association of MAC address and VLAN
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