MDS213 Datasheet, PDF (42/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
10.0 The Control Bus
The CPU Interface, or Control Bus, provides the communication path between the system CPU and all other key
components within the MDS213 (i.e. the HISC). It operates in two modes: managed mode, where it utilizes an
external CPU, and unmanaged mode, where an external CPU does not exist.
In Managed mode, the CPU Interface provides the communication path between the systems' external CPU and
the HISC, Frame Buffer Memory (SRAM) or another MDS213. See Figure 11.
Control Bus
MDS213
MDS213
CPU
Flash
Memory
Figure 11 - CPU Interface Configuration in Managed Mode
In unmanaged mode, the CPU Interface provides the communication path between the Switch Devices and Flash
Memory, and between any two MDS213 Switches. See Figure 12.
Control Bus
Primary DEV
MDS213
Arbitrator
Secondary DEV
MDS213
Flash
Memory
Figure 12 - Control Bus Configuration in Unmanaged Mode
10.1 External CPU Support
The control bus comprises of a 32-bit wide CPU bus and supports Big and Little Endian CPU byte ordering. The
standard microprocessors supported include:
• Intel 486 CPUs
• Motorola MPC860 and 801 CPUs
• Intel i960Jx CPU
• MIPS processor with minimum conversion
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