MDS213 Datasheet, PDF (40/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
(4 bytes) and a falling (negative) edge at the beginning of the last double word of an XPipe message as shown in
Figure 10.
Note: The negative edge does not occur at the end of the last double word, but instead, at the beginning of the last
double word. This allows XPipe messages to be sent consecutively (back-to-back).
.
Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 ......... Last Cycle Idle
X_CLKI/O
X_DENI/O
*1
X_DI/O[31:0]
D Word 0 D Word 1 D Word 2 D Word 3 ^.........
.........
......... _{D Word N}
Note 1: Positive edge at the beginning of the first Double Word.
Negative edge at the beginning of the last Double Word.
Figure 10 - Basic Timing Diagram of XPipe
9.0 Physical Layer (PHY) Interface
The Physical Layer Interface is designed to interface Zarlink chipsets to a variety of Physical Layer devices.
Reduced Media Independent Interface (RMII) is used for 10/100 interfaces, while Gigabit connections can use
either Gigabit Media Independent Interfaces (GMII) or Ten Bit Interface (TBI).
The chip ball names for the MAC use M as the first letter of the name, followed by their pin number, and then their
function. For example, M1_RXD0 refers to Mac port 1, receive data 0 of the receive data pair.
9.1 Reduced MII (RMII)
The MDS213 implements the Reduced Media Independent Interface (RMII) signals, REF_CLK, CRS_DV, RXD
[1:0], TX_EN, and TXD [1:0], defined in Section 5 of the RMII Consortium Specification. The purpose of this
interface is to provide a low cost alternative to the IEEE 802.3u [2] MII interface. Under IEEE 802.3u [2] an MII
comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such
as switches, the number of pins can add significant cost as the port counts increase. Zarlink MDS213 offer 12 or 24
ports, in one or two devices respectively. At 6 pins per port and 1 pin per switch ASIC, the RMII specification saves
119 pins plus the extra power and ground pins to support those additional pins for a 12 port switch ASIC.
Architecturally, the RMII specification provides for an additional reconciliation layer on either side of the MII but can
be implemented in the absence of an MII. The management interface (MDIO/MDC) is assumed to be identical to
that defined in IEEE 802.3u [2].
The RMII supports both 10 and 100Mbps data rates across a two bit Transmit Data (TXD) path and a two bit
Receive Data (RXD) path.
The RMII uses a single synchronous clock reference sourced from the Media Access Controller (MAC), or an
external clock source, to the Physical Layer (PHY). Doubling the clock frequency to 50 MHz allows a reduction of
required data and control signals, thereby providing a low cost alternative to the IEEE Std 802.3u Media
Independent Interface (MII). The RMII functions to make the differences between copper and optical PHYs
transparent to the MAC sublayer.
The RMII specification has the following characteristics:
• It is capable of supporting 10Mbps and 100Mbps data rates
• A single clock reference is sourced from the MAC to PHY (or from an external source)
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Zarlink Semiconductor Inc.