MDS213 Datasheet, PDF (24/120 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps + 1Gbps Ethernet Switch

MDS213
Data Sheet
3.0 The Media Access Control (MAC) and GIGABIT (GMAC)
The MDS213 MAC/GMAC contains twelve Fast Ethernet MACs and one Gigabit Ethernet MAC, defined by the
IEEE Standard 802.3 CSMA/CD. Each Fast Ethernet MAC is connected to a Physical Layer (PHY) via the Reduced
Media Independent Interface (RMII), and the Gigabit Ethernet MAC is connected to a PHY via the Gigabit Media
Independent Interface (GMII) or the Ten Bit Interface (TBI). The MAC/GMAC sublayer ("MAC/GMAC") consists of a
Transmit and Receive section and is responsible for data encapsulation/ decapsulation. Data encapsulation/
decapsulation involves framing (frame alignment and frame synchronization), handling source and destination
addresses, and detecting physical medium transmission errors. The MAC/GMAC also manages half-duplex
collisions, including collision avoidance and contention resolution (collision handling). The MDS213 includes an
optional MAC Control sublayer ("MAC Control") used for IEEE Flow Control functions.
During frame transmission, the MAC transmit section encapsulates the data by prepending a preamble and a Start
of Frame Delimiter (SFD), inserts a destination and source address, and appends the Frame Check Sequence
(FCS) for error detection. In VLAN aware switches, the MAC/GMAC inserts, replaces, or removes VLAN Tags from
these frame formats based on instructions from the Search Engine. When necessary, the MAC/GMAC regenerates
the Frame Check Sequence and performs "padding" for frames less than 64 bytes.
During frame reception, the MAC receive section verifies that the CRC is valid, de-serializes the data, and buffers
the frame into the Receive FIFO. The MAC/GMAC then signals the Frame Engine, using Receive Direct Memory
Access (RxDMA), that data is available in the FIFO and is ready for storage.
3.1 MAC/GMAC Configuration
MAC/GMAC operations are configured through the global Device Configuration Register (DCR2) and/or the
MAC/GMAC Control and Configuration Registers (ECR0, ECR1), defined in the Register Definition Section of the
MDS213 data sheet. The default settings for Autonegotiation, flow control, frame length, and duplex mode may be
changed and configured by the user on a per-port basis, either in hardware or software.
3.2 The Inter-frame Gap
The Inter-frame Gap (IFG), defined as 96 bit times, is the interval between successive Ethernet frames for the
MAC/GMAC. Depending on traffic conditions, the measurement reference for the IFG changes. If a frame is
successfully transmitted without a collision, the IFG measurement starts from the de-assertion of the Transmit
Enable (TXEN) signal. However, if a frame suffers a collision, the IFG measurement starts from the deassertion of
the Carrier Sense (CRS) signal.
3.3 Ethernet Frame Limits
A legal Ethernet frame size, defined by the IEEE specification, must be between 64 and 1518 bytes, referring to the
packet length on the wire. For transmitting or forwarding frames whose data lengths do not meet the minimum
requirements, the MAC/GMAC appends extra bytes (padding) from the PAD field. Frames, longer than the
maximum length may either be forwarded or discarded, depending on the register configuration. Although the
MAC/GMAC may be configured to forward oversized frames in the Device Configuration Register (DCR2), the
frame buffers' maximum size of 1536 bytes cannot be exceeded. For VLAN Aware systems, the maximum frame
size is increased from 1518 bytes to 1522 bytes to accommodate the 4-byte VLAN Tag.
3.4 Collision Handling and Avoidance
In half duplex mode, if multiple stations on the same network attempt to transmit at the same time, interference
could occur causing a collision. The MAC/GMAC monitors the Carrier Sense (CRS) signal to determine if the
medium is available before attempting to transmit data. If the transmission medium is busy, the MAC/GMAC defers
(delays) its own transmissions to decrease the load on the network. This is called collision avoidance.
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