XC5000 Datasheet, PDF (9/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

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VersaRing I/O Interface
The interface between the IOBs and core logic has been
redesigned in the XC5200 family. The IOBs are
completely decoupled from the core logic. The XC5200
IOBs contain dedicated boundary-scan logic for added
board-level testability, but do not include input or output
registers. This approach allows a maximum number of
IOBs to be placed around the device, improving the I/O-to-
gate ratio and decreasing the cost per I/O. A “freeway” of
interconnect cells surrounding the device forms the
VersaRing, which provides connections from the IOBs to
the internal logic These incremental routing resources
provide abundant connections from each IOB to the
nearest VersaBlock, in addition to Longline connections
surrounding the device. The VersaRing eliminates the
historic trade-off between high logic utilization and pin
placement flexibility. These incremental edge resources
give users increased flexibility in preassigning (i.e.,
locking) I/O pins before completing their logic designs.
This ability accelerates time-to-market, since PCBs and
other system components can be manufactured
concurrent with the logic design.
General Routing Matrix
The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight
coupling to the logic resources contained in the
VersaBlocks. Advanced simulation tools were used during
the development of the XC5200 architecture to determine
the optimal level of routing resources required. The
XC5200 family contains six levels of interconnect
hierarchy — a series of single-length lines, double-length
lines, and Longlines all routed through the GRM. The
direct connects, LIM, and logic-cell feedthrough are
contained within each VersaBlock. Throughout the
XC5200 interconnect, an efficient multiplexing scheme, in
combination with TLM, was used to improve the overall
efficiency of silicon usage.
Performance Overview
The XC5200 family has been benchmarked with many
designs running synchronous clock rates up to 40 MHz. The
performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the interconnect
routing. Table 4 shows some performance numbers for
representative circuits, using worst-case timing parameters
for the Engineering Sample (ES) speed grade. A rough
estimate of timing can be made by assuming 6 ns per logic
level, which includes direct-connect routing delays. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.
Table 4. Performance for Several Common Circuit Functions
Function
16-bit Decoder from Input Pad
24-bit Accumulator
16-to-1 Multiplexer
16-bit Unidirectional Loadable Counter
16-bit U/D Counter
16-bit Adder
24-bit Loadable U/D Counter
XC5200 Speed Grade
-6
-5
-4
9 ns
8 ns
32 MHz
39 MHz
16 ns
13 ns
40 MHz
50 MHz
40 MHz
50 MHz
24 ns
20 ns
36 MHz
42 MHz
5