XC5000 Datasheet, PDF (30/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Preliminary
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade -6
-5
-4
Description
Symbol Device
Max
(ns)
Max
(ns)
Max
(ns)
Global Signal Distribution
From pad through global buffer, to any clock (CK)
T_BUFG
XC5202
XC5204
XC5206 9.4
8.8
XC5210 9.4
8.8
XC5215
Internal Clock to Output Pad Delay
From clock (CK) to output pad (fast), using direct connect
between Q and output (O)
T_OKPOF
XC5202
XC5204
XC5206 9.9
8.9
XC5210 9.9
8.9
XC5215
From clock (CK) to output pad (slew-limited), using direct
connect between Q and output (O)
T_OKPOS
XC5202
XC5204
XC5206 14.8
12.7
XC5210 14.8
12.7
XC5215
Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
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