XC5000 Datasheet, PDF (6/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Preliminary (v1.0)
XC5200 Family Compared to XC4000 Family
For those readers already familiar with the XC4000 family
of Xilinx Field-Programmable Gate Arrays, here is a
concise description of the similarities and differences
between the XC4000 and XC5200 families.
Superficially, the XC5200 family is quite similar to the
XC4000 family. Both use CMOS SRAM technology. Both
use 4-input lookup tables with unshared inputs. Both have
a dedicated fast carry track, and dedicated boundary-scan
logic in the input/output blocks (IOBs).
XC5200 and XC4000 devices are footprint and pin-out
compatible; their pin names and pin locations are
identical. XC5200 devices offer the same configuration
options as XC4000 devices, and they can be intermixed
with XC4000 devices in a configuration daisy chain.
There are also, however, significant differences between
the two families:
• XC5200 lookup tables cannot be used as RAM.
• The XC5200 family offers dedicated carry logic, but
differs from the XC4000 family in that the sum is
generated in an additional function generator in the
adjacent column. An XC5200 device thus uses twice as
many function generators for adders, subtracters,
accumulators, and some counters. Note, however, that
a loadable up/down counter requires the same number
of function generators in both families.
• XC5200 devices have no dedicated wide edge
decoders. The XC5200 carry logic, unlike the XC4000
architecture, can be used to cascade function
generators to implement wide AND and OR functions,
for example.
• The XC5200 family contains a flexible coupling of logic
and local routing resources called the VersaBlock. The
XC5200 VersaBlock element includes the Configurable
Logic Block (CLB), a Local Interconnect Matrix (LIM),
and direct connects to neighboring VersaBlocks.
• XC5200 CLBs are roughly equivalent to two XC4000
CLBs. Each XC5200 CLB contains four 4-input function
generators and four registers, which are configured as
four independent Logic Cells™ (LCs). The output from
each function generator can be brought out as a CLB
output and/or drive the D input of a flip-flop. Pairs of
logic cells can be combined to form a 5-input function
generator.
• There are four direct feedthrough paths per CLB, one
per LC. These paths can provide extra data input lines
or serve as local routes without consuming any logic
resources.
• The XC5200 family has a global reset, whereas the
XC4000 family has both a global set and a global reset.
• Unlike the XC4000 family, each register can be
configured as either an edge-triggered D flip-flop or a
transparent, level-sensitive latch.
• There are no dedicated IOB flip-flops, but there are fast
direct connects to adjacent CLBs.
Table 2. Four Generations of Xilinx Field-Programmable Gate Array Families
Parameter
Function generators per CLB
Logic inputs per CLB
Logic outputs per CLB
Low-skew global buffers
User RAM
Dedicated decoders
Cascade chain
Fast carry logic
Internal 3-state drivers
IEEE boundary scan
Output slew-rate control
Power-down option
Crystal oscillator circuit
XC5200
4
20
12
4
no
no
yes
yes
yes
yes
yes
no
no
XC4000
3
9
4
8
yes
yes
no
yes
yes
yes
yes
no
no
XC3000A/XC3100A
2
5
2
2
no
no
no
no
yes
no
yes
yes
yes
XC2000
2
4
2
2
no
no
no
no
no
no
no
yes
yes
2