XC5000 Datasheet, PDF (22/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
DATA BUS
PROGRAM
INIT
M0 M1 M2
+5V
5K
CS1
D0-D7
DOUT
XC5200
PROGRAM
INIT
CCLK
Preliminary
+5V
M0 M1 M2
CS1
DOUT
D0-D7
Optional
Daisy-Chained
XC5200
PROGRAM
INIT
CCLK
To Additional
Optional
Daisy-Chained
Devices
CCLK
Figure 15. Express Mode
X6153
To Additional
Optional
Daisy-Chained
Devices
Express Mode
The Express mode (see Figure 15) is similar to the Slave
serial mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An
external source is used to drive CCLK while byte-wide
data is loaded directly into the configuration data shift
registers. In this mode the XC5200 family is capable of
supporting a CCLK frequency of 10 MHz, which is
equivalent to an 80-MHz serial rate, because eight bits of
configuration data are being loaded per CCLK cycle. An
XC5210 in the Express mode, for instance, can be
configured in about 2 ms. The Express mode does not
support CRC error checking, but does support constant-
field error checking.
In the Express configuration mode, an external signal
drives the CCLK input(s) of the LCA device(s). The first
bytes of parallel configuration data must be available at
the D inputs of the LCA devices a short set-up time before
each rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge. See
Figure 16.
The Express mode is only supported by the XC5200
family. It may not be used, therefore, when an XC5200
device is daisy-chained with devices from other Xilinx
families.
If the first device is configured in the Express mode,
additional devices may be daisy-chained only if every
device in the chain is also configured in the Express
mode. CCLK pins are tied together and D7-D0 pins are
tied together for all devices along the chain. A status
signal is passed from DOUT to CS1 of successive devices
along the chain. The lead device in the chain has its CS1
input tied High (or floating, since there is an internal pull-
up). All devices receive and recognize the preamble and
length count, but frame data is accepted only when CS1 is
High and the device’s configuration memory is not already
full. The status pin DOUT is pulled LOW two internal-
oscillator cycles (nominally 1 MHz per cycle) after INIT is
recognized as High, and remains Low until the device’s
configuration memory is full. Then DOUT is pulled High to
signal the next device in the chain to accept the
configuration data on the D7-D0 bus.
How to Delay Configuration After Power-Up
For details on how to delay configuration after power-up,
refer to page 2-32 of the 1994 Xilinx Programmable Logic
Data Book.
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