XC5000 Datasheet, PDF (14/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Preliminary (v1.0)
Cascade Function
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be
configured to take advantage of these four cascaded
CY_MUXes. Note that AND and OR cascading are
specific cases of a general decode. In AND cascading all
bits are decoded equal to logic one, while in OR
cascading all bits are decoded equal to logic zero. The
flexibility of the LUT achieves this result.
cascade out
CO
DI
A15 F4
A14 F3
A13 F2 AND
A12 F1
CY_MUX
DI
A11 F4
A10 F3
A9
F2 ^AND
A8
F1
CY_MUX
DO
out
D
Q
FD
X
LC3
DO
D
Q
FD
X
LC2
DI
A7 F4
A6 F3
A5 F2 ^AND
A4 F1
CY_MUX
DI
A3 F4
A2 F3
A1 F2 AND
A0 F1
CY_MUX
CI
cascade in
DO
D
Q
FD
X
LC1
DO
D
Q
FD
CE CK
X
CLR LC0
CY_MUX
F=0
Initialization of
carry chain (One Logic Cell)
X5708
Figure 7. XC5200 CY_MUX Used for Decoder Cascade Logic
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