XC5000 Datasheet, PDF (11/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

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Design Implementation
The design implementation tools satisfy the requirements
for an automated design process. Logic partitioning, block
placement, and signal routing are performed by the PPR
program. The partitioner takes the logic from the entered
design and maps the logic into the architectural resources
of the FPGA (such as the logic blocks, I/O blocks, and 3-
state buffers). The placer then determines the best
locations for the blocks, depending on their connectivity
and the required performance. The router finally connects
the placed blocks together.
The PPR algorithms support fully automatic
implementation of most designs. However, for demanding
applications, the user may exercise various degrees of
control over the automated implementation process.
Optionally, user-designated partitioning, placement, and
routing information can be specified as part of the design-
entry process. The implementation of highly structured
designs can benefit greatly from the basic floorplanning
techniques familiar to designers of large gate arrays.
The PPR program includes XACT-Performance, a feature
that allows designers to specify the timing requirements
along entire paths during design entry. Timing path
analysis routines in PPR then recognize and
accommodate the user-specified requirements. Timing
requirements can be entered on the schematic in a form
directly relating to the system requirements (such as the
targeted minimum clock frequency, or the maximum
allowable delay on the data path between two registers).
So, while the timing of each individual net is not
predictable, the overall performance of the system along
entire signal paths is automatically tailored to match user-
generated specifications.
Design Verification
The high development cost associated with common
mask-programmed gate arrays necessitates extensive
simulation to verify a design. Due to the custom nature of
masked gate arrays, mistakes or last-minute design
changes cannot be tolerated. A gate-array designer must
simulate and test all logic using simulation software.
Simulation describes what happens in a system under
worst-case situations. However, simulation can be tedious
and slow, and simulation vectors must be generated. A
few seconds of system time can take weeks to simulate.
Programmable-gate-array users, however, can use in-
circuit debugging techniques in addition to simulation.
Because Xilinx devices are reprogrammable, designs can
be verified in real time without the need for extensive
simulation vectors.
The XACT development system supports both simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from
the design database. This data can then be sent to the
simulator to verify timing-critical portions of the design
database using XDELAY, the Xilinx static timing analyzer
tool. Back-annotation — the process of mapping the
timing information back into the signal names and
symbols of the schematic — eases the debugging effort.
For in-circuit debugging, the XACT development system
includes a serial download and readback cable
(XChecker) that connects the FPGA in the system to the
PC or workstation through an RS232 serial port. The
engineer can download a design or a design revision into
the system for testing. The designer can also single-step
the logic, read the contents of the numerous flip-flops on
the device, and observe internal logic levels. Simple
modifications can be downloaded into the system in a
matter of minutes.
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