XC5000 Datasheet, PDF (38/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Top
Preliminary (v1.0)
Left
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18
R2C1
R2C18
R3C1
R3C18
R4C1
R5C1
R6C1
R4C18
R5C18
R6C18
R7C1
R8C1
R9C1
R10C1
R11C1
R7C18
R8C18
R9C18
R10C18
R11C18
R12C1
R13C1
R14C1
R12C18
R13C18
R14C18
R15C1
R16C1
R17C1
R15C18
R16C18
R17C18
R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
Right
Bottom
KEY:
I/O Pad
R#C# _{CLB, identified by R#C# = row and column numbers}
Figure 20. XC5210 CLB-to-Pad Relationship
34