XC5000 Datasheet, PDF (33/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

R
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade -6
-5
-4
Description
Symbol
Max
(ns)
Max
(ns)
Max
(ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay)
Pad to I (with delay)
T_PI
5.4
4.9
T_PID
11.1
10.2
Output
Propagation Delays to CMOS or TTL Levels
Output (O) to Pad (fast)
Output (O) to Pad (slew-limited)
3-state to Pad active (fast)
3-state to Pad active (slew-limited)
Internal GTS to Pad active (fast)
Internal GTS to Pad active (slew-limited)
T_OPF
T_OPS
T_TSONF
T_TSONS
T_GTSF
T_GTSS
4.6
9.4
6.9
11.6
17.7
22.3
4.5
8.3
6.6
10.4
15.9
19.7
Note:
1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce,
see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book.
2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
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