XC5000 Datasheet, PDF (5/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200
R
Logic Cell Array Family
Preliminary (v1.0)
Product Description
Features
• High-density family of Field-Programmable Gate Arrays
(FPGAs)
• Design- and process-optimized for low cost
— 0.6-µm three-layer metal (TLM) process
• System performance up to 50 MHz
• SRAM-based, in-system reprogrammable architecture
• Flexible architecture with abundant routing resources
— VersaBlock™ logic module
— VersaRing™ I/O interface
— Dedicated cell-feedthrough path
— Hierarchical interconnect structure
— Extensive registers/latches
— Dedicated carry logic for arithmetic functions
— Cascade chain for wide input functions
— Dedicated IEEE 1149.1 boundary-scan logic
— Internal 3-state bussing capability
— Four global low-skew clock or signal distribution nets
— Globally selectable CMOS or TTL input thresholds
— Output slew-rate control
— 8-mA sink current per output
• Configured by loading binary file
— Unlimited reprogrammability
— Six programming modes, including high-speed
Express™ mode
• 100% factory tested
• 100% footprint compatibility for common packages
• Fully supported by XACT^® Development System
— Includes complete support for XACT-Performance™,
X-BLOX™, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker™
— Wide selection of PC and workstation platforms
— Interfaces to more than 100 third-party CAE tools
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for TLM
technology and 0.6-µm CMOS SRAM process, dramatic
advances have been made in silicon efficiency. These
advances position the XC5200 family as a cost-effective,
high-volume alternative to gate arrays.
Building on experiences gained with three previous
successful SRAM FPGA families, the XC5200 family
brings a robust feature set to high-density programmable
logic design. The VersaBlock logic module, the VersaRing
I/O interface, and a rich hierarchy of interconnect
resources combine to enhance design flexibility and
reduce time-to-market.
Complete support for the XC5200 family is delivered
through the familiar XACT software environment. The
XC5200 family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and
synthesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200 devices.
Table 1. Initial XC5200 Field-Programmable Gate Array Family Members
Device
Typical Gate Range
VersaBlock Array
Number of CLBs
Number of Flip-Flops
Number of I/Os
TBUFs per Horizontal Longline
XC5202
2,200 -
2,700
8x8
64
256
84
10
XC5204
3,900 -
4,800
10 x 12
120
480
124
14
XC5206
6,000 -
7,500
14 x 14
196
784
148
16
XC5210
10,000 -
12,000
18 x 18
324
1,296
196
20
XC5215
14,000 -
18,000
22 x 22
484
1,936
244
24
1