XC5000 Datasheet, PDF (20/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Preliminary
Global Lines
Two pairs of horizontal and vertical global lines provide
low-skew clock signals to the CLBs. Global lines are
driven by low-skew buffers inside the VersaRing. The
global lines provide direct input only to the CLB clock pins.
The global lines also connect to the General Routing
Matrix to provide access from these lines to the function
generators and other control signals.
Four clock input pads at the corners of the chip, as shown
in Figure 12, provide a high-speed, low-skew clock
network to each of the four global-line buffers. In addition
to the dedicated pad, the global lines can be sourced by
internal logic. PIPs from several routing channels within
the VersaRing, inside the IOI cell, can also be configured
to drive the global-line buffers.
VersaRing Input/Output Interface
The VersaRing, shown in Figure 13, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The
VersaRing decouples the pad ring’s pitch from the core’s
pitch. Each VersaRing Cell provides up to four pad-cell
connections on one side, and connects directly to the CLB
ports on the other side. Depending on placement and pad-
cell pitch, any number of pad cells to a maximum of four
can be connected to a VersaRing cell. Note: there are no
direct connects from the Pads on top and bottom edges.
Input/Output Pad
The I/O pad, shown in Figure 14, consists of an input buffer
and an output buffer. The output driver is an 8-mA full-rail
CMOS buffer with 3-state control. Two slew-rate control
modes are supported to minimize bus transients. Both the
output buffer and the 3-state control are invertible.
The input buffer has globally selected CMOS and TTL
input thresholds. The input buffer is invertible and also
provides a programmable delay line to assure reliable
chip-to-chip set-up and hold times. Minimum ESD
protection is 5 KV using the Human Body Model.
VersaRing
2
8
8
8
2
2
2
Pad
GRM
10
Pad
Interconnect
Pad
4
VersaBlock
4
Pad
GRM
8
2
2
10
4
VersaBlock
4
2
8
2
8
Interconnect
8
Pad
Pad
Pad
Pad
X5705
Figure 13. VersaRing I/O Interface
GCK1
GCK4
GCK2
Figure 12. Global Lines
Vcc
PAD
GCK3
X5704
Figure 14. XC5200 I/O Block
I
O
T
X4964
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