|
XC5000 Datasheet, PDF (28/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays | |||
|
◁ |
XC5200 Logic Cell Array Family
Preliminary
Pin Descriptions
LDC
Low During Conï¬guration is driven Low until conï¬guration
completes. It is available as a control output indicating that
conï¬guration is not yet completed. After conï¬guration, this
is a user-programmable I/O pin.
INIT
Before and during conï¬guration, this is a bidirectional
signal. An external pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low
during the power stabilization and internal clearing of the
conï¬guration memory. As an active-Low input, it can be
used to hold the LCA device in the internal WAIT state
before the start of conï¬guration. Master-mode devices
stay in a WAIT state an additional 30 to 300 µs after INIT
has gone High.
During conï¬guration, a Low on this output indicates that a
conï¬guration data error has occurred. After conï¬guration,
this is a user-programmable I/O pin.
GCK1 - GCK4
Four Global Inputs each drive a dedicated internal global
net with short delay and minimal skew. If not used for this
purpose, any of these pins is a user-programmable I/O
pin.
CS0, CS1, WS, RS
These four inputs are used in peripheral modes. The chip
is selected when CS0 is Low and CS1 is High. While the
chip is selected, a Low on Write Strobe (WS) loads the
data present on the D0 - D7 inputs into the internal data
buffer; a Low on Read Strobe (RS) changes D7 into a
status output: High if Ready, Low if Busy, and D0â¦D6 are
active Low. WS and RS should be mutually exclusive, but
if both are Low simultaneously, the Write Strobe overrides.
After conï¬guration, these are user-programmable I/O
pins.
A0 - A17
During Master Parallel mode, these 18 output pins
address the conï¬guration EPROM. After conï¬guration,
these are user-programmable I/O pins.
D0 - D7
During Master Parallel and peripheral conï¬guration
modes, these eight input pins receive conï¬guration data.
After conï¬guration, they are user-programmable I/O pins.
DIN
During Slave Serial or Master Serial conï¬guration modes,
this is the serial conï¬guration data input receiving data on
the rising edge of CCLK.
During parallel conï¬guration modes, this is the D0 input.
After conï¬guration, DIN is a user-programmable I/O pin.
DOUT
During conï¬guration in any mode, this is the serial
conï¬guration data output that can drive the DIN of daisy-
chained slave LCA devices. DOUT data changes on the
falling edge of CCLK, 1.5 CCLK periods after it was
received at the DIN input. After conï¬guration, DOUT is a
user-programmable I/O pins.
Unrestricted User-Programmable I/O Pins
I/O
A pin that can be conï¬gured to be input and/or output after
conï¬guration is completed. Before conï¬guration is
completed, these pins have an internal high-value pull-up
resistor that deï¬nes the logical level as High.
Before and during conï¬guration, all outputs that are not used for the conï¬guration process are 3-stated with a
50-k⦠to 100-k⦠pull-up resistor.
24
|
▷ |