XC5000 Datasheet, PDF (12/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Detailed Functional Description
CLB Logic
Figure 3 shows the logic in the XC5200 CLB, which
consists of four Logic Cells (LC[3:0]). Each Logic Cell
consists of an independent 4-input Lookup Table (LUT),
and a D-Type flip-flop or latch with common clock, clock
enable, and clear, but individually selectable clock polarity.
Additional logic features provided in the CLB are:
• High-speed carry propagate logic.
• High-speed pattern decoding.
• High-speed direct connection to flip-flop D-inputs.
• Each flip-flop can be programmed individually as either
a transparent, level-sensitive latch or a D flip-flop.
• Four 3-state buffers with a shared Output Enable.
• Two 4-input LUTs can be combined to form an
independent 5-input LUT.
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
Preliminary (v1.0)
CO
DI
I1
I2
F4
F3
I3
F2 F
I4
F1
F5_MUX
I5
DI
DO
D
Q
FD
X
LC1
DO
D
Q
F4
F3
F2 F
F1
FD
CI
CE CK
5-Input Function
X
CLR ^LC0
Figure 5. Two LUTs in Parallel Combined to Create a 5-input Function
8
out
Qout
X5710