XC5000 Datasheet, PDF (24/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
Table 6. Unified XC5200 Bitstream Format
Data Type
Value
Fill Byte
11111111
Preamble
11110010
Length Counter
COUNT(23:0)
Fill Byte
11111111
Start Byte
11111110
Data Frame *
DATA(N-1:0)
Cyclic Redundancy Check or
Constant Field Check
CRC(3:0) or
0110
Fill Nibble
1111
Extend Write Cycle
FFFFFF
Postamble
11111110
Fill Bytes (30)
FFFF…FF
Legend:
(unshaded) Only once per bitstream
(light)
Once per data frame
(dark)
Once per device
Table 7. Internal Configuration Data Structure
Device
VersaBlock
Array
PROM
Size
(bits)
Xilinx
Serial Prom
Needed
XC5202
8x8
42,448
XC1765
XC5204
10 x 12
70,736
XC1728
XC5206
14 x 14
106,320
XC17128
XC5210
18 x 18
165,520
XC17256
XC5215
22 x 22
237,776
XC17256
Bits per Frame = (34 x number of Rows) + 28 for the
top + 28 for the bottom + 4 splitter bits + 8 start bits + 8
error check bits + 4 fill bits + 4 extended write bits
Number of Frames = (12 x number of Columns) + 7 for
the left edge + 8 for the right edge + 1 splitter bit
Program Data = (Bits per Frame x Number of Frames)
+ 48 header bits + 8 postamble bits + 280 fill bits
PROM Size = Program Data
Preliminary
Boundary Scan
Instructions
Available:
VCC
No
3V
Yes
EXTEST*
SAMPLE/PRELOAD*
BYPASS
CONFIGURE*
(*only when PROGRAM = High)
Generate
One Time-Out Pulse
of 4 ms
PROGRAM
= Low
Yes
Completely Clear
Configuration
Memory
~1.3 µs per Frame
INIT
No
High? if
Master
Yes
Master CCLK
Goes Active after
50 to 250 µs
Sample
Mode Lines
Load One
Configuration
Data Frame
SAMPLE/PRELOAD
BYPASS
Frame ^Yes
Error
No
Pull INIT Low
and Stop
Config-
uration
No
memory
Full
Yes
Pass
Configuration
Data to DOUT
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
CCLK
Count Equals
No
Length
Count
Yes
Start-Up
Sequence
F
Operational
If Boundary Scan
is Selected
Figure 17. Start-up Sequence
X6037
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